Case study · 2025 · Automotive · Manufacturing
Test-Bench Telemetry for an EV Component Lab
An EV component lab was testing motor controllers and battery modules with a museum of instruments: separate loggers per signal type, clocks that never quite agreed, and days of channel mapping before each campaign. We built them a unified acquisition platform — FPGA-based capture with deterministic, microsecond-aligned timestamps across 32 channels, gateway firmware streaming to a live console, and a Python toolkit their engineers script analyses in.
Screens are illustrative recreations — client interfaces stay confidential.
The challenge
Correlating a current transient against a temperature event across two loggers with drifting clocks was archaeology, not analysis — engineers spent more time aligning exports than interpreting them.
Test campaigns lost days to setup: hand-wired channel maps, per-instrument configs, and a calibration ritual that had to be repeated whenever anything moved between the six rigs.
What we built
Acquisition in the fabric
Capture, filtering, and timestamping implemented on an Artix-7-class FPGA — 32 synchronized channels sustained at 1 MS/s with hardware-clocked timestamps, so alignment is a property of the design rather than a post-processing step.
Firmware built for streaming
C/C++ gateway firmware moves framed capture data over the lab network with backpressure and loss accounting — a saturated link degrades detectably, never silently.
Configuration as files, not folklore
Channel maps, ranges, and trigger conditions are versioned configuration applied per campaign — moving a test between rigs means loading a profile, and setup dropped from two days to about three hours.
Analysis where engineers live
A Python toolkit reads captures natively with the timestamp model built in, plus a live web console for in-progress runs — trigger review happens during the test, not the morning after.
The results
- 32 ch @ 1 MS/s
- Sustained acquisition
- <1 µs
- Timestamp jitter
- 3 hrs
- Campaign setup time
synchronized across all channels
cross-channel alignment, hardware-clocked
down from ~2 days of manual configuration
- 32 channels sustained at 1 MS/s with timestamp jitter under 1 µs across channels — cross-signal correlation became a one-liner.
- Test campaign setup fell from roughly two days to three hours, and usable test hours per rig rose 60% over five months.
- The lab retired four instrument types and their export-alignment tooling; one platform now covers the six rigs.
Client identities stay confidential; figures are rounded from end-of-engagement delivery reporting.
Stack & expertise
- Artix-7-class FPGA (VHDL)
- C / C++ firmware
- Python toolkit
- web console
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